25-01-2013, 12:43 AM
Sir,where can i get the VHDL code for that topic? Also i'm not able to get most of the reference papers. from where shall i get those. Hope you reply soon.
-Thank You
kesma
25-01-2013, 12:43 AM
Sir,where can i get the VHDL code for that topic? Also i'm not able to get most of the reference papers. from where shall i get those. Hope you reply soon. -Thank You kesma
25-01-2013, 09:40 AM
to get information about the topic "A Low-Power Single-Phase Clock Multiband Flexible Divider"related topic refer the link bellow https://seminarproject.net/Thread-power-...nm-technol
27-05-2014, 04:31 PM
A Low-Power Single-Phase Clock Multiband Flexible Divider
A Low-Power Single-Phase .pdf (Size: 325.75 KB / Downloads: 43) Abstract In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18- m CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4–2.484 GHz, 5.15–5.35 GHz, and 5.725–5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply. INTRODUCTION WIRELESS LAN (WLAN) in the multigigahertz bands, such as HiperLAN II and IEEE 802.11a/b/g, are recognized as leading standards for high-rate data transmissions, and standards like IEEE 802.15.4 are recognized for low-rate data transmissions. The demand for lower cost, lower power, and multiband RF circuits increased in conjunction with need of higher level of integration. The frequency synthesizer, usually implemented by a phase-locked loop (PLL), is one of the power-hungry blocks in the RF front-end and the first-stage fre- quency divider consumes a large portion of power in a frequency syn- thesizer. The integrated synthesizers for WLAN applications at 5 GHz reported in [1] and [2] consume up to 25 mW in CMOS realizations, where the first-stage divider is implemented using an injection-locked divider which consumes large chip area and has a narrow locking range. The best published frequency synthesizer at 5 GHz consumes 9.7 mW at 1-V supply, where its complete divider consumes power around 6 mW [3], where the first-stage divider is implemented using the source-coupled logic (SCL) circuit [4], which allows higher operating frequencies but uses more power. Dynamic latches are faster and consume less power compared to static dividers. The TSPC [5] and E-TSPC [6] designs are able to drive the dynamic latch with a single clock phase and avoid the skew problem [5]. However, the adoption of single-phase clock latches in frequency dividers has been limited to PLLs with applications below 5 GHz [7], [8]. MULTIMODULUS 32/33/47/48 PRESCALER The proposed wideband multimodulus prescaler which can divide the input frequency by 32, 33, 47, and 48 is shown in Fig. 4. It is similar to the 32/33 prescaler used in [7], but with an additional inverter and a multiplexer. The proposed prescaler performs additional divisions (di- vide-by-47 and divide-by-48) without any extra flip-flop, thus saving a considerable amount of power and also reducing the complexity of multiband divider which will be discussed in Section V. CONCLUSION In this paper, a wideband 2/3 prescaler is verified in the design of proposed wide band multimodulus 32/33/47/48 prescaler. A dynamic logic multiband flexible integer- divider is designed which uses the wideband 2/3 prescaler [17], multimodulus 32/33/47/48 prescaler, and is silicon verified using the 0 18 m CMOS technology. Since the mul- timodulus 32/33/47/48 prescaler has maximum operating frequency of 6.2 GHz, the values of - and -counters can actually be programmed to divide over the whole range of frequencies from 1 to 6.2 GHz with finest resolution of 1 MHz and variable channel spacing. However, since interest lies in the 2.4- and 5–5.825-GHz bands of operation, the - and -counters are programmed accordingly. The proposed multiband flexible divider also uses an improved loadable bit-cell for Swallow -counter and consumes a power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, and provides a solution to the low power PLL synthesizers for Bluetooth, Zigbee, IEEE 802.15.4, and IEEE 802.11a/b/g WLAN applications with variable channel spacing. |
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