01-05-2012, 11:57 AM
DESIGN AND SIMULATION OF 4-BIT UP/DOWN COUNTER
THEORY:
A binary counter has an outputthat increment its decimal-equivalent value by 1 with every clock pulse. Counters do not need any inputs other than the clock Ø although it is possible to add control inputs. In this counter different inputs have been given depending upon the number of bits, mainly we deal with the 2-bit and 4-bit counter according to which we select the number of inputs and outputs.
For the 2- bit word counter two outputs are present i.e A1 and A0 cycles from 00 to 11 and then starts automatically. The firststep in determining the logic operation is to write the logic equation.
Similarly we do for the 4- bit counter in which it has the direction and also the clock, when the direction and clock is 1 it will counts the functions otherwise not.
VHDL CODE OF 4-BIT UP/DOWN COUNTER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10m is
Port ( CK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter10m;
architecture Behavioral of counter10m is
signalCOUNT_INTtd_logic_vector(3 downto 0):="0000";
begin
process(CK,DIRECTION)
begin
if(CK='1' and CK'event)then
if (DIRECTION='1')then
COUNT_INT<=COUNT_INT+1;
else
COUNT_INT<=COUNT_INT-1;
end if;
end if;
end process;
COUNT_OUT<=COUNT_INT;
end Behavioral;
CONCLUSION:
After getting the test bench waveform and RTL schematic of the required experiment (4-bit up/down counter) the program is successfully downloaded to the FPGA kit.