29-01-2013, 03:12 PM
DESIGN OF SHIFT REGISTER(TO VERIFY SERIAL TO PARALLEL,PARALLEL TO SERIAL,SERIAL TO SERIAL,PARALLEL TO PARALLEL)USING FLIP-FLOPS
DESIGN OF SHIFT REGISTER.docx (Size: 11.66 KB / Downloads: 19)
Aim:-
To study shift register using IC 7495 in all its modes i.e.
SIPO/SISO, PISO/PIPO.
Apparatus: - IC 7495, etc.
Procedure :
Serial In Parallel Out(SIPO):
1. Connections are made as per circuit diagram.
2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to
QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the
shift register.
Serial In Serial Out (SISO):
1. Connections are made as per circuit diagram.
2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at
QD. Thus the data applied serially at the input comes out serially at QD
Parallel In Serial Out (PISO):
1. Connections are made as per circuit diagram.
2. Apply the desired 4 bit data at A, B, C and D.
Result:
shift registers using IC 7495 in all its modes i.e.SIPO/SISO, PISO/PIPO are verified.