22-04-2014, 04:59 PM
Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems
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Abstract
Recent developments in the field of reconfigurable SoC
devices (FPGAs) will enable the development of embedded
systems where software tasks, running on a CPU, can coex-
ist with hardware tasks. We devised a real-time computing
architecture that can integrate hardware and software exe-
cutions in a transparent manner, and can support real-time
QoS adaptation by means of partial reconfiguration of mod-
ern FPGA devices. Tasks are allowed to migrate seamlessly
from CPU to FPGA and vice versa to support dynamic QoS
adaptation and cope with dynamic workloads. In this pa-
per, we discuss the design and implementation of an on-chip
infrastructure, OS extensions and task design methodology
that enable hardware-software transparency in the presence
of relocation. The overall architecture is suitable to sched-
ule real-time workloads and we derive bounds on reloca-
tion overhead. Finally, we show the applicability of our de-
sign methodology on a concrete task design case.
Introduction
Recently emerging SoC devices enable the development
of embedded systems where software tasks, running on a
CPU, can coexist with hardware tasks running on a re-
configurable device (FPGA). Such hybrid platforms are es-
pecially suitable for the development of real-time embed-
ded systems because they combine the flexibility of soft-
ware execution on a CPU with timing predictability and
high performance of hardware execution on a Partially Re-
configurable Device (PRD).
System Model
In our model, each task τi in the system can be provided
in multiple configurations {τi0 , τi1 , . . . , τij , . . .}, which pro-
vide similar functionality at different QoS levels. Configu-
rations can be either software or hardware; a task can pro-
vide both but is not required to. A software configuration
(or SW task for simplicity) is a portion of code running on
the CPU with associated data. A hardware configuration (or
HW task for simplicity) is a logical function that has been
synthesized for execution on the PRD. Every configuration
τij is periodically activated with period pj
i and has dead-
line equal to its period; note that two SW or two HW con-
figurations can be functionally equivalent and differ only in
their period. For convenience τi0 is defined as a special null
configuration: it represents the fact that the task is not run-
ning in the system. Typically, HW configurations will run
at higher frequencies than SW configurations thanks to the
speedup achieved by hardware implementation. Therefore,
when the system is not under heavy load all tasks with a
HW configuration will be run in hardware. If the load on
the system increases and the reconfigurable area is filled,
some tasks will have to be moved to SW (see Section 4 for
details on reconfiguration management).
Memory Layout
As introduced in Section 1, we base our transparency
mechanism on a shared memory architecture. An advan-
tage of this choice is that the software compilation model
and memory layout of the OS require minimal changes.
We make no assumption on software task loading, i.e. tasks
can be either preloaded with the OS image or the OS can
provide an executable loader/relocator with dynamic load-
ing capabilities; note that even if tasks are preloaded, they
can still be activated dynamically at run-time. We believe
that our description is general enough to be applicable to
most embedded OSs using a Unix-like task memory map-
ping and employing the ELF executable file format. Fur-
thermore, note that our description is largely independent
from the choice of a specific CPU, as our only major re-
quirement is support for both external and software inter-
rupts. Both cached and non cached CPUs can be supported.
Note that the CPU used in our system, a MicroBlaze soft-
core [32], does not include a memory management unit. The
system can be extended to support memory virtualization by
imposing suitable constraints on the memory mapping and
page replacement policy for shared memory areas; however,
for simplicity we omit such mechanisms from our descrip-
tion.
Reconfiguration Management
Our OS design includes a reconfiguration manage-
ment layer that keeps track of task configurations and
enforces timing constraints by performing on-line schedu-
lability analysis and admission control. Tasks are log-
ically grouped into applications, that are collections
of data-dependent tasks. At any time, each applica-
tion uses one of possibly several different execution modes.
A mode specifies a single configuration for each task com-
prising the application. For example, a video encoding
application could specify two modes with different encod-
ing frequency. In this case, configurations with different
frequencies will be selected for each task in the applica-
tion, and some tasks could be required to be executed in
hardware in the fastest frequency mode. Note that if an ap-
plication is not required to run in the system at all times, it
can specify so with a mode comprised of null task configu-
rations.
Related Work
The problem of providing HW-SW transparency to re-
locatable tasks has first been addressed by Mignolet, Nol-
let et al. in [19, 18, 22]. Their system model differs from
ours in some important points. First of all, it uses a message
passing communication model based on an on-chip packet-
switching network. This design choice constraints tasks to a
fixed dimension and furthermore imposes a high area over-
head to implement the required packet routers. Second, they
do not provide any standardized and reusable abstraction to
preserve the task state between migration, which severely
complicates the application developer’s job. Finally, the sys-
tem does not minimize the relocation jitter and does not take
into account any real-time constraint in the analysis
Conclusions
Thanks to the development and rapid improvements of
SoC devices, hybrid systems that incorporate both soft-
ware processors and hardware reconfigurable modules on
the same chip are becoming increasingly attractive, espe-
cially for demanding real-time applications. In this context,
we believe that employing a multitasking model for both the
SW and HW elements can significantly simplify develop-
ment by making use of a familiar abstraction at the highest
level. Furthermore, relocation is a required feature to obtain
a flexibility of use similar to the one provided by general
purpose processing units. In this paper, we designed a full
SoC architecture, including HW interfaces and OS mecha-
nisms, that supports standardized abstractions for commu-
nication transparency and real-time task relocation. As a
proof of concept, we implemented the designed architec-
ture on a FPGA device and developed relocatable tasks us-
ing the provided abstractions.