29-03-2014, 12:19 PM
II B. Tech II Semester, Regular Examinations, April/May – 2013 SWITCHING THEORY AND LOGIC DESIGN
Regular Examinations.pdf (Size: 245.77 KB / Downloads: 47)
1. a) Perform the binary subtraction for the following using 1’s compliment method.
i) 28-8 ii) 30-25
iii) 25.5-12.25
iv) 10.625 - 8.75
b) Perform the following subtraction operations using 2’s compliment.
i) (111001)2-(101011)2
ii) (1111)2-(1010)2
iii) (112)10-(65)10
iv) (100.5)10-(50.75)10
(7M+8M)
2. a) Find the compliments of the following
i) xy’+x’y
ii) (AB’+C)D’+E
iii) (ABC)’(A+B+C)
iv) AB’C+A’BC+ABC
b) Simplify the following algebra expressions
i) x’+y’+xyz’
ii) A+A’B+A’B’C+A’B’C’D
iii) BC+C’D’+ABD’
iv) w’x’+x’y’+x’z’+yz
(7M+8M)
3. Simplify the following Boolean function by using tabulation method.
F ( A, B, C , D) = Σ m (0,1,2,5,7,8,9,10,13,15)
4.
5.
a) Implement Full adder circuit using ROM and verify the working.
b) Design a half adder and subtractor using suitable gates.
(15M)
(8M+7M)
a) Implement the following functions using a decoder.
f 1 ( x, y, z ) = Σ m (0,1,3,7)
f 2 ( x, y, z ) = Σ m (2,3,7)
b) Design a full subtractor circuit with decoder.