09-10-2012, 02:31 PM
VERILOG HDL IEEE STD 1364
VERILOG.pptx (Size: 391.26 KB / Downloads: 31)
Introduction.
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL).
A hardware description Language is a language used to describe a digital system, for example, a microprocessor or a memory or a simple flip-flop.
This just means that, by using a HDL one can describe any hardware (digital ) at any level.
HISTORY
Verilog was started initially as a proprietary hardware modeling language by Gateway Design Automation Inc. around 1984.
Verilog simulator was first used beginning in 1985 and was extended substantially through 1987.The implementation was the Verilog simulator sold by Gateway.
After many years, new features have been added to Verilog, and new version is
called Verilog 2001.
SIMULATION
Simulation is the process of verifying the functional characteristics of models
We use simulators to simulate the Hardware models.
To test if the RTL code meets the functional requirements of the specification, see if all the RTL blocks are functionally correct.
SYNTHESIS
Simulation is the process in which the synthesis tools takes the RTL code to the target technology.
It maps RTL codes to the gates & primitives and do minimal amount of timing analysis.
Example: Xillinx ISE, QuatrusII.
VERILOG SYNTAX
Verilog is free-format language. White space can be used freely.
Verilog is CASE Sensitive
User provided names are called identifiers and should start with a “letter” or “_” example: CONUT_1
Predefined identifiers are called keywords. All keywords are lower case. Example: assign, module, begin, end, etc.,
Comments- two forms: /* first form*/ & // second form
Value set: 1(high), 0(low), X(unknown), Z(high impedance).