26-12-2012, 02:21 PM
Verilog: always Blocks
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Introduction
Sections 1.1 to 1.6 discuss always@ blocks in Verilog, and when to use the two major flavors of always@
block, namely the always@( * ) and always@(posedge Clock) block.
1.1 always@ Blocks
always@ blocks are used to describe events that should happen under certain conditions. always@ blocks
are always followed by a set of parentheses, a begin, some code, and an end. Program 1 shows a skeleton
always@ block.
always@(posedge Clock) Blocks
always@(posedge Clock) (“always at the positive edge of the clock”) or always@(negedge Clock) (“always
at the negative edge of the clock”) blocks are used to describe Sequential Logic, or Registers.
Only <= (non-blocking) assignments should be used in an always@(posedge Clock) block. Never use =
(blocking) assignments in always@(posedge Clock) blocks. Only use always@(posedge Clock) blocks when
you want to infer an element(s) that changes its value at the positive or negative edge of the clock.
For example, consider Figure 1, a recreation of Program 2 that uses posedge Clock as its sensitivity
list. Figure 1 is also known as a shift register. The completed always@ block is shown in Program 4.
Pitfalls
You might be wondering what happens if you don’t follow the conventions set forth in Sections 1.4 and
1.5. The following are some easy-to-make mistakes in Verilog that can have a dramatic [and undesired]
effect on a circuit.
1. Consider the shift register from Figure 1. If you place = assignments inside of an always@(posedge
Clock) block to produce the shift register, you instead get the parallel registers shown in Figure 3
and Program 7. You might also get one register, whose output is tied to B, C and D. Both possible outcomes are equivelent. These circuit make sense, but don’t create shift registers! (As shift
registers are common construct, we assume that you wanted to create a shift register)