25-10-2012, 04:22 PM
CMOS Full-Adders for Energy-Efficient Arithmetic Applications in DSP
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I. INTRODUCTION
Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. The necessity of designing high speed and low power arithmetic circuits suitable for computationally intensive applications has motivated the design of a high performance arithmetic unit. Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This module is the core of many arithmetic operations such as addition/subtraction, multiplication, division and address generation.
PREVIOUS FULL-ADDER OPTIMIZATIONS
Many papers have been published regarding the optimization of low-power full-adders, trying different options for the logic style(standard CMOS [2], differential cascode voltage switch (DCVS) [3], complementary pass-transistor logic (CPL) [4], double pass-transistor logic (DPL) [5], swing restored CPL (SR-CPL) [6], and hybrid styles[6]), and the logic structure used to build the adder module. The internal logic structure shown in Fig. 1has been adopted as the standard configuration in most of the enhancements developed for the 1-bit full-adder module. In this configuration, the adder module is formed by three main logical blocks: a XOR-XNOR gate to obtain A XOR B, and complement of A xor B ( a x nor b)(Block 1), and XOR blocks or multiplexers to obtain the SUM (So) and CARRY (Co) outputs (Blocks 2 and 3).A deep comparative study to determine the best implementation for Block 1was presented in [5], and an important conclusion was pointed out in that work:
APPLICATION
The designed full adder is decided to use in the place where the addition of partial product takes place in the multiplier. This application work is under process. This is to be verified using Xilinx.