04-04-2012, 01:23 PM
SIMULATION OF PARALLEL ADDER
Parallel Adder.doc (Size: 38 KB / Downloads: 35)
AIM:
To design and simulate the pipelined parallel adder to add eight 12bit numbers using 2’s complement.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a verilog file
• Assign port names
• Write verilog program
• Check syntax
• Create a test bench waveform and give input
• Simulate the parallel adder using ISE simulator
THEORY:
Parallel adder is an adder which adds all the n-bits of
m-numbers at a time. Two’s compliment of a binary number is calculated as follows,
• Take a binary number which is having one more bit then the number for which we are going to find 2’s compliment.
• The MSB of the number should be one and the LSB of the number should be zero.
• To get 2’s compliment we have to subtract the two numbers.
• After finding the 2’s compliment we have to add all the numbers.
• Take 2’s compliment for the above result to get original result.
PROGRAM:
Code:
module PADD(sum, carry);
output [11:0] sum;
output [2:0] carry;
reg [11:0] sum;
reg [2:0] carry;
//8 Inputs each of 12 Bits
reg [11:0] in1 = 12'b000000000001; // 001
reg [11:0] in2 = 12'b000000000001; // 001
reg [11:0] in3 = 12'b000000000001; // 001
reg [11:0] in4 = 12'b000000000001; // 001
reg [11:0] in5 = 12'b000000000010; // 002
reg [11:0] in6 = 12'b000000000010; // 002
reg [11:0] in7 = 12'b000000000010; // 002
reg [11:0] in8 = 12'b000000000010; // 002
//Temporary Signals
reg [12:0] a1, a2, a3, a4, a5, a6, a7, a8;
reg [12:0] temp = 13'b1000000000000;
reg [15:0] temp1 = 16'b1000000000000000;
reg [14:0] c = 15'b000000000000000;
reg [14:0] res = 15'b000000000000000;
always @ (temp,in1,in2,in3,in4,in5,in6,in7,in8,temp1,a1, a2,
a3, a4, a5, a6, a7, a8,res,c)
begin
a1 <= temp - in1; // 2's complement of in1
a2 <= temp - in2; // 2's complement of in2
a3 <= temp - in3; // 2's complement of in3
a4 <= temp - in4; // 2's complement of in4
a5 <= temp - in5; // 2's complement of in5
a6 <= temp - in6; // 2's complement of in6
a7 <= temp - in7; // 2's complement of in7
a8 <= temp - in8; // 2's complement of in8
end
//Adding 2's Complement Datas
c<= a1+a2+a3+a4+a5+a6+a7+a8;
//Again 2's complement the added data to get original value
res<= temp1 - c;
sum<= res[11:0]; //12 Bit Sum output
carry<= res[14:12]; //3 Bit Carry output
end
endmodule
RESULT:
Thus the simulation of pipelined parallel adder using 2’s complement has been executed and the output was verified.