04-04-2012, 01:29 PM
PLACE AND ROUTE AND BACK ANNOTATION
PLACE AND ROUTE AND BACKANNOTATION.doc (Size: 130 KB / Downloads: 26)
AIM:
To study the place and route and back annotation algorithm for FPGA using 4*1 multiplexer.
APPARATUS REQUIRED:
• XILINX ISE 9.2i software
• PC with Windows-XP
ALGORITHM:
• Create a new verilog file
• Assign port name
• Write verilog HDL code for 4*1 multiplexer.
• Check syntax
• Run place and route tool to assign pin location for each port
• Using view or edit routed design to change the assigned pin locations.
• View the locked pin locations.
THEORY:
It is the translation of routed and fitted design to a timing simulation net list. To define the behavior at the FPGA, a hardware description language or a schematic design automatic [EDA] to technology mapped net list is generated. The net list can then be fitted to the actual FPGA architecture using a process called place & route. Finally the design is said out in FPGA at which point propagation delay can be added and the simulation run again with this value annotated on the net list.
PROGRAM:
Code:
module route(i0, i1, i2, i3, s0, s1, y);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output y;
reg y;
always @(i0 or i1 or i2 or i3 or s0 or s1)
begin
case({s0,s1})
2'b00: y=i0;
2'b01: y=i1;
2'b10: y=i2;
2'b11: y=i3;
endcase
end
endmodule
RESULT:
Place and route was used to modify and filter the reassignment at pin relocation of slices and run time minimized.
LOGIC DIAGRAM: