10-04-2013, 03:24 PM
D FLIP-FLOP(IC 7474)
ABSTRACT:
To study and simulate D FLIP-FLOP using VHDL.
THEORY:
The 74 is a dual positive edge triggered D type flip flop featuring individual data, clock, set and reset inputs; also complementary Qn, Qn bar. The asynchronous set and reset pins are PR_L and CLR_L these inputs operate independent of clock. Information on the data D input is transferred to the Qn output on the low to high transition of the clock pulse.
PROCEDURE:
Logical gate D Flip-flop Design is entered through VHDL.
Simulate the design by applying test vectors-pr_l, clr_l, clk, d and observing outputs q and qn.
It is required to lock the pins and give timing constraints.
Implement the design by passing the design by various stages by mapping, time analysis and bit stream. For locking the pins write UCF file before implementation and guide the same through option set control files. Output of the implementation is .JED file, which can be directly programmed into target device FPGA.
The last step is programming in which the programme can physically download the architecture from computer to target device FPGA