13-04-2013, 04:18 PM
VERIFICATION OF FLIP FLOPS
AIM:
To verify the truth tables of RS, D, JK and T flip flops using digital logic gates.
THEORY:
SEQUENTIAL CIRCUITS
The present output depends upon the present input and previous output. The sequential
circuits are formed from combinational circuit by adding a memory element.
FLIP FLOPS
A Flip Flop is also called as – 1 bit memory cell (or) Bistable Multivibrator. Flip flop is a
sequential circuit which can maintain a binary state indefinitely until the power is delivered to the
circuit and the input signal changes its states.
RS FLIP FLOP
A clocked RS Flip Flop consists of a basic NOR flip-flop and two AND gates. The outputs of two AND gates remain zero as long as the clock pulse is zero, regardless of the S and R inputs. When the clock pulse (CP) goes to 1, information from the S and R input is allowed to reach the basic flip flop. The set state is reached with S=1, R=0 and CP=1. To change to clear state inputs must be S=0, R=1 and CP=1. When S=1, R=1 and if CP=1 or 0, the state of flip-flop is indeterminate.
D FLIP FLOP
The D flip-flop is a modification of RS flip-flop. The NOR gates form the basic flip-Flop. The D input goes directly to S input and its complement is applied to R input. When the CP is 0, the output of the AND gates are zero irrespective of any inputs. When CP=0 or 1 and D=1;
JK Flip Flop
JK flip-flop is designed to as a refinement to the indeterminate state occurring in RS flip-flop. The inputs J and K behave as S and R inputs. When the inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, that is if Q=1, it switches to Q=0. The output Q is ANDed with K and CP inputs, so that the flip-flop is cleared during a clock pulse only if Q=1 previously. Similarly, the output Q' is ANDed with J and CP inputs, so that the flip-flop is set with a clock pulse only if Q'=1 previously.
T Flip Flop
T flip-flop is a single input version of JK flip-flop. The T flip flop is obtained by combining the J and K inputs together. Regardless of the present state of the flip-flop, it assumes the complement state when CP occurs while input T is at logic 1.T flip-flop is also called as TOGGLE flip-flop.
PROCEDURE:
1. Connections are given as per the circuit diagram on the bread board.
2. The power supply is switched ON and set a voltage of 5 Volts.
3. If the input to be given to a gate is logic ‘1’ then it is connected to +5 Volts and if the input to be given to the gate is logic ‘0’ then the particular input terminal is connected to ground.
4. Truth tables of flip flops are verified.
5. If the output is logic ‘1’ then the LED glows, if the output is logic ‘0’ then the LED does not glow.