13-10-2012, 10:38 AM
Pipelined architecture
pipelined architecture.pdf (Size: 82.19 KB / Downloads: 26)
The MC68020/EC020 contains a three-word instruction
pipe where instruction opcodes are decoded.
As shown in Figure 1-5, instruction words enter the pipe
at stage B and proceed to stages C
and D. Each stage has a status bit that reflects
whether the word in the stage was loaded with
data from a bus cycle that was terminated
abnormally.
Stages of the pipe are only filled in response to specific
prefetch requests issued by the sequencer.
Words are loaded into the instruction pipe
from the cache holding register.
individual stages of the pipe
16 bits wide
cache holding register
32 bits wide and contains the entire long word
long word is obtained from the instruction
cache or the external bus in response to a
prefetch request from the sequencer