11-07-2012, 04:34 PM
Dataflow VHDL
dataflow_vhdl (1).ppt (Size: 73.5 KB / Downloads: 34)
Bit Vectors
Signals can be more than one bit (a vector)
Represent P address and data, function selection, etc.
Declaration is similar to single bit signals
Type is bit_vector or std_logic_vector
We also must specify vector index range and direction
big endian: (low to high)
little endianhigh downto low)
Vector Logical Operations
Single bit logical operations also apply to vectors
Operands MUST be the same size (generally applies to all vector operations)
Assignment target must also have the same number of bits as the result
Operations are applied bitwise to operands to produce the vector result
Vector Arithmetic Operations
Vector arithmetic operations are basically the same as vector logical operations
Operands MUST be the same size
Assignment target must also have the same number of bits as the result
Operations are applied bitwise to operands to produce the vector result
The only difference is the carry or borrow
Carry in/out must be specially handled
Result can be 1 bit larger than operands (CO)
Multiplication and VHDL
Again, for arithmetic operations
Operands MUST be the same size
Assignment target must also have the same number of bits as the result
However, for multiplication (*) what is not stated is that the result of the operation is twice the size of the operands